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CONTRIBUTIONS/MOSS 2.2/Z80LIB/Z80.DOC
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CONTRIBUTIONS/MOSS 2.2/Z80LIB/Z80.DOC
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Z-80 Macro Library Documentation
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--------------------------------
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I.
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The purpose of this library is to enable the assembly of the Z-80
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instruction set on a CP/M sytem using the CP/M MAC macro assembler.
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This library is invoked with the pseudo-op:
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" MACLIB Z80 "
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II.
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The following symbols and notations are used in the individual macro
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descriptions;
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r - Any of the 8 bit registers: A, B, C, D, E, H, L, or M
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rr - Any of the 16 bit register pairs: BC, DE, HL, or SP
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nn - 8 bit immediate data (0 through 255)
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d - 8 bit signed displacment (-128 through +127)
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nnnn - 16 bit address or immediate data (0 through 65535)
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b - bit number (0-7, 7 is most significant, 0 is least)
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addr - 16 bit address within PC+127 through PC-128
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m(zzz) - Memory at address "zzz"
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III.
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MACLIB ver. Zilog ver TDL ver
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-------------- ------------- -------------
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LDX r,d LD r,(IX+d) MOV r,d(IX)
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Load register from indexed memory (with IX)
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LDY r,d LD r,(IY+d) MOV r,d(IY)
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Load register from indexed memory (with IY)
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STX r,d LD (IX+d),r MOV d(IX),r
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Store register to indexed memory (with IX)
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STY r,d LD (IY+d),r MOV d(IY),r
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Store register to indexed memory (with IY)
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MVIX nn,d LD (IX+d),nn MVI d(IX)
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Move immediate to indexed memory (with IX)
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MVIY nn,d LD (IY+d),nn MVI d(IY)
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Move immediate to indexed memory (with IY)
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LDAI LD A,I LDAI
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Move I to A
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LDAR LD A,R LDAR
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Move R to A
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STAI LD I,A STAI
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Move A to I
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STAR LD R,A STAR
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Move A to R
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LXIX nnnn LD IX,nnnn LXI IX,nnnn
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Load IX immediate (16 bits)
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LXIY nnnn LD IY,nnnn LXI IY,nnnn
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Load IY immediate (16 bits)
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LBCD nnnn LD BC,(nnnn) LBCD nnnn
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Load BC direct (from memory at nnnn)
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LDED nnnn LD DE,(nnnn) LDED nnnn
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Load DE direct
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LSPD nnnn LD SP,(nnnn) LSPD nnnn
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Load SP direct
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LIXD nnnn LD IX,(nnnn) LIXD nnnn
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Load IX direct
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LIYD nnnn LD IY,(nnnn) LIYD nnnn
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Load IY direct
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SBCD nnnn LD (nnnn),BC SBCD nnnn
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Store BC direct (to memory at nnnn)
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SDED nnnn LD (nnnn),DE SDED nnnn
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Store DE direct
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SSPD nnnn LD (nnnn),SP SSPD nnnn
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Store SP direct
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SIXD nnnn LD (nnnn),IX SIXD nnnn
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Store IX direct
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SIYD nnnn LD (nnnn),IY SIYD nnnn
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Store IY direct
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SPIX LD SP,IX SPIX
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Copy IX to the SP
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SPIY LD SP,IY SPIY
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Copy IY to the SP
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PUSHIX PUSH IX PUSH IX
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Push IX into the stack
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PUSHIY PUSH IY PUSH IY
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Push IY into the stack
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POPIX POP IX POP IX
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Pop IX from the stack
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POPIY POP IY POP IY
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Pop IY from the stack
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EXAF EX AF,AF' EXAF
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Exchange AF and the alternate, AF'
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EXX EXX EXX
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Exchange BC DE HL with BC' DE' HL'
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XTIX EX (SP),IX XTIX
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Exchange IX with the top of the stack
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XTIY EX (SP),IY XTIY
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Exchange IY with the top of the stack
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LDI LDI LDI
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Move m(HL) to m(DE), increment DE and HL, decrement BC
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LDIR LDIR LDIR
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Repeat LDI until BC = 0
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LDD LDD LDD
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Move m(HL) to m(DE), decrement HL, DE, and BC
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LDDR LDDR LDDR
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Repeat LDD until BC = 0
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CCI CPI CCI
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Compare A with m(HL), increment HL, decrement BC
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CCIR CPIR CCIR
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Repeat CCI until BC = 0 or A = m(HL)
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CCD CPD CCD
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Compare A with m(HL), decrement HL and BC
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CCDR CPDR CCDR
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Repeat CCD until BC = 0 or A = m(HL)
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ADDX d ADD (IX+d) ADD d(IX)
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Indexed add to A
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ADDY d ADD (IY+d) ADD d(IY)
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Indexed add to A
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ADCX d ADC (IX+d) ADC d(IX)
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Indexed add with carry
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ADCY d ADC (IY+d) ADC d(IY)
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Indexed add with carry
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SUBX d SUB (IX+d) SUB d(IX)
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Indexed subtract
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SUBY d SUB (IY+d) SUB d(IY)
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Indexed Subtract
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SBCX d SBC (IX+d) SBB d(IX)
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Indexed subtract with "borrow"
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SBCY d SBC (IY+d) SBB d(IY)
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Indexed subtract with borrow
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ANDX d AND (IX+d) ANA d(IX)
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Indexed logical and
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ANDY d AND (IY+d) ANA d(IY)
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Indexed logical and
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XORX d XOR (IX+d) XRA d(IX)
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Indexed logical exclusive or
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XORY d XOR (IY+d) XRA d(IY)
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Indexed logical exclusive or
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ORX d OR (IX+d) ORA d(IX)
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Indexed logical or
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ORY d OR (IY+d) ORA d(IY)
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Indexed logical exclusive or
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CMPX d CP (IX+d) CMP d(IX)
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Indexed compare
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CMPY d CP (IY+d) CMP d(IY)
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Index compare
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INRX d INC (IX+d) INR d(IX)
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Increment memory at m(IX+d)
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INRY d INC (IY+d) INR d(IY)
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Increment memory at m(IY+d)
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DCRX d INC (IX+d) INR d(IX)
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Decrement memory at m(IX+d)
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DCRY d DEC (IY+d) DCR d(IY)
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Decrement memory at m(IX+d)
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NEG NEG NEG
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Negate A (two's complement)
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IM0 IM0 IM0
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Set interrupt mode 0
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IM1 IM1 IM1
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Set interrupt mode 1
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IM2 IM2 IM2
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Set interrupt mode 2
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DADC rr ADC HL,rr DADC rr
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Add with carry rr to HL
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DSBC rr SBC HL,rr DSBC rr
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Subtract with "borrow" rr from HL
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DADX rr ADD IX,rr DADX rr
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Add rr to IX (rr may be BC, DE, SP, IX)
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DADY rr ADD IY,rr DADY rr
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Add rr to IY (rr may be BC, DE, SP, IY)
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INXIX INC IX INX IX
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Increment IX
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INXIY INC IY INX IY
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Increment IY
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DCXIX DEC IX DCX IX
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Decrement IX
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DCXIY DEC IY DCX IY
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Decrement IY
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BIT b,r BIT b,r BIT b,r
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Test bit b in register r
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SETB b,r SET b,r SET b,r
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Set bit b in register r
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RES b,r RES b,r RES b,r
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Reset bit b in register r
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BITX b,d BIT b,(IX+d) BIT b,d(IX)
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Test bit b in memory at m(IX+d)
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BITY b,d BIT b,(IY+d) BIT b,d(IY)
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Test bit b in memory at m(IY+d)
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SETX b,d SET b,(IX+d) SET b,d(IX)
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Set bit b in memory at m(IX+d)
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SETY b,d SET b,(IY+d) SET b,d(IY)
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Set bit b in memory at m(IY+d)
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RESX b,d RES b,(IX+d) RES b,d(IX)
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Reset bit b in memory at m(IX+d)
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RESY b,d RES b,(IY+d) RES b,d(IY)
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Reset bit b in memory at m(IY+d)
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JR addr JR addr-$ JMPR addr
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Jump relative unconditional
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JRC addr JR C,addr-$ JRC addr
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Jump relative if Carry indicator true
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JRNC addr JR NC,addr-$ JRNC addr
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Jump relative if carry indicator false
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JRZ addr JR Z,addr-$ JRC addr
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Jump relative if Zero indicator true
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JRNZ addr JR NZ,addr-$ JRNZ addr
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Jump relative if Zero indicator false
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DJNZ addr DJNZ addr-$ DJNZ addr
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Decrement B, jump relative if non-zero
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PCIX JMP (IX) PCIX
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Jump to address in IX ie, Load PC from IX
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PCIY JMP (IY) PCIY
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Jump to address in IY
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RETI RETI RETI
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Return from interrupt
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RETN RETN RETN
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Return from non-maskable interrupt
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INP r IN r,(C) INP r
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Input from port C to register r
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OUTP r OUT (C),r OUTP r
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Output from register r to port (C)
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INI INI INI
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Input from port (C) to m(HL), increment HL, decrement b
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INIR INIR INIR
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Input from port (C) to m(HL), increment HL, decrement B, repeat if B <> 0
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OUTI OTI OUTI
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Output from m(HL) to port (C), increment HL, decrement B
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OUTIR OTIR OUTIR
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Repeat OUTI until B = 0
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IND IND IND
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Input from port (C) to m(HL), decrement HL & B
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INDR INDR INDR
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Repeat IND until B = 0
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OUTD OTD OUTD
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Output from m(HL) to port (C), decrement HL & B
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OUTDR OTDR OUTDR
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Repeat OUTD until B = 0
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RLCR r RLC r RLCR r
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Rotate left circular register
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RLCX d RLC (IX+d) RLCR d(IX)
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Rotate left circular indexed memory
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RLCY d RLC (IY+d) RLCR d(IY)
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Rotate left circular indexed memory
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RALR r RL r RALR r
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Rotate left arithmetic register
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RALX d RL (IX+d) RALR d(IX)
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Rotate left arithmetic indexed memory
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RALY d RL (IY+d) RALR d(IY)
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Rotate left arithmetic indexed memory
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RRCR r RRC r RRCR r
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Rotate right circular register
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RRCX d RRC (IX+d) RRCR d(IX)
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Rotate right circular indexed
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RRCY d RRC (IY+d) RRCR d(IY)
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Rotate right circular indexed
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RARR r RR r RARR r
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Rotate right arithmetic register
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RARX d RR (IX+d) RARR d(IX)
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Rotate right arithmetic indexed memory
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RARY d RR (IY+d) RARR d(IY)
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Rotate right arithmetic indexed memory
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SLAR r SLA r SLAR r
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Shift left register
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SLAX d SLA (IX+d) SLAR d(IX)
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Shift left indexed memory
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SLAY d SLA (IY+d) SLAR d(IY)
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Shift left indexed memory
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SRAR r SRA r SRAR r
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Shift right arithmetic register
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SRAX d SRA (IX+d) SRAR d(IX)
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Shift right arithmetic indexed memory
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SRAY d SRA (IY+d) SRAR d(IY)
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Shift right arithmetic indexed memory
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SRLR r SRL r SRLR r
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Shift right logical register
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SRLX d SRL (IX+d) SRLR d(IX)
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Shift right logical indexed memory
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SRLY d SRL (IY+d) SRLR d(IY)
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Shift right logical indexed memory
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RLD RLD RLD
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Rotate left digit
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RRD RRD RRD
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Rotate right digit
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HK ?D
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DB 0FDH, 0CBH, ?D, 16H
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ENDM
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RRCR MACRO ?R
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DB 0CBH, 08H + ?R
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ENDM
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RRCX MACRO ?D
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@CHK ?D
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DB 0DDH, 0CBH, ?D, 0EH
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ENDM
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RRCY MACRO ?D
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@CHK ?D
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DB 0FDH, 0CBH, ?D, 0EH
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ENDM
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RARR MACRO ?R
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DB 0CBH, 18H + ?R
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ENDM
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RARX MACRO ?D
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