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title 'Hardware Interrupts'
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;****************************************
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; *
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; HARDWARE INTERRUPTS *
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; Last changed : 2/16/84 *
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; *
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;****************************************
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NP_8087 equ 1 ; will xios support 8087
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; 1 -- yes
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; 0 -- no
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CPMDEBUG equ 1 ; 1 = turn off I3 int's for debug envir.
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; 0 = I3 int's are on - normal envir.
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MASTER_PIC_PORT equ 50H
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SLAVE_PIC_PORT equ 52H
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; Specific End Of Interrupt Commands
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CI0_EOI EQU 67H ; Specific EOI master/slave
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CO0_EOI EQU 66H ; Specific EOI master/slave
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I3_CI_EOI EQU 62H ; Specific EOI master only
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I3_CO_EOI EQU 63H ; Specific EOI master only
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HD_EOI EQU 61H ; specific eoi master only
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FLPY_EOI EQU 64H ; Specific EOI master only
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TICK_EOI EQU 61H ; Specific EOI master/slave
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NP_8087_EOI EQU 60H ; Specific EOI master/slave
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SLAVE_EOI EQU 67H ; Specific EOI master only
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DISABLE_INTS EQU 0FFH ; mask to turn off all interrupts
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MASTER_INT_MASK EQU 063H ; floppies, transmit and
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; receive for interfacer 3,
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; and slave pic
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SLAVE_INT_MASK EQU 07CH ; receive interrupts, 8087
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; and the timer tick
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NS_EOI EQU 20H ; Non specific end of interrupt
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MASTER_ICW_1 EQU 1DH ; basic operational mode of chip
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MASTER_ICW_2 EQU 40H ; base of chips interrupt vectors
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MASTER_ICW_3 EQU 80H ; master/slave map
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MASTER_ICW_4 EQU 01H ; interrupt response mode
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SLAVE_ICW_1 EQU MASTER_ICW_1
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SLAVE_ICW_2 EQU MASTER_ICW_2 + 8
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SLAVE_ICW_3 EQU 07H ; slave I.D. number
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SLAVE_ICW_4 EQU MASTER_ICW_4
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I3_INT_ENABLE EQU 0FFH
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; Character interrupt vectors
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;
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MASTER_INT_BASE equ 40H
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SLAVE_INT_BASE equ 48H
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CONIN_IR equ 7 ; on the slave
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CONOUT_IR equ 6 ; on the slave
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I3_IN_IR equ 2 ; on the master
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I3_OUT_IR equ 3 ; on the master
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HD_IR equ 1 ; on the master
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FLPY_IR equ 4 ; on the master
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TICK_IR equ 1 ; on the slave
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NP_8087_IR equ 0 ; on the slave
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CON_IN_OFF EQU ( SLAVE_INT_BASE + CONIN_IR ) * 4
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CON_IN_SEG EQU CON_IN_OFF + 2
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CON_OUT_OFF EQU ( SLAVE_INT_BASE + CONOUT_IR ) * 4
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CON_OUT_SEG EQU CON_OUT_OFF + 2
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I3_IN_OFF EQU ( MASTER_INT_BASE + I3_IN_IR ) * 4
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I3_IN_SEG EQU I3_IN_OFF + 2
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I3_OUT_OFF EQU ( MASTER_INT_BASE + I3_OUT_IR ) * 4
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I3_OUT_SEG EQU I3_OUT_OFF + 2
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FLPY_OFF EQU ( MASTER_INT_BASE + FLPY_IR ) * 4
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FLPY_SEG EQU FLPY_OFF + 2
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H_DISK_OFF EQU ( MASTER_INT_BASE + HD_IR ) * 4
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H_DISK_SEG EQU H_DISK_OFF + 2
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TICK_OFF EQU ( SLAVE_INT_BASE + TICK_IR ) * 4
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TICK_SEG EQU TICK_OFF + 2
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NP_8087_OFF EQU ( SLAVE_INT_BASE + NP_8087_IR ) * 4
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NP_8087_SEG EQU NP_8087_OFF + 2
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cseg
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public hard_int_vec
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public pic_init
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public int_enable
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public reset_tick_pic
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public reset_sstint_pic
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public reset_i3tint_pic
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public reset_ssiint_pic
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public reset_i3iint_pic
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extrn conin_int:near
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extrn sst_int:near ; public in ssint.a86
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extrn i3r_int:near
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extrn i3t_int:near ; public in i3int.a86
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extrn h_disk_int:near ; public in hdisk.a86
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extrn flint:near ; public in fd.a86
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extrn tick_int:near ; public in tick.a86
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if NP_8087
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extrn np_8087_int:near
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public reset_8087_pic
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endif
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;==============
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reset_tick_pic:
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;==============
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;
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; reset the PIC for the tick.
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mov al, SLAVE_EOI
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out MASTER_PIC_PORT, al
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mov al, TICK_EOI
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out SLAVE_PIC_PORT, al
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ret
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if NP_8087
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;=============
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reset_8087_pic:
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;=============
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;
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; reset the PIC for the 8087
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mov al, SLAVE_EOI
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out MASTER_PIC_PORT, al
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mov al, NP_8087_EOI
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out SLAVE_PIC_PORT, al
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ret
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endif
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;=============
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reset_ssiint_pic:
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;=============
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; Reset System Support Board's PIC for receive
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;
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mov al, SLAVE_EOI ;; clear the PICS for this interrupt
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out MASTER_PIC_PORT, al ;; request channel
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mov al, CI0_EOI
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out SLAVE_PIC_PORT, al
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ret
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;===============
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reset_sstint_pic:
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;===============
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;
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; Reset System support board USART's PIC for transmit
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mov al, SLAVE_EOI ;; reset the PIC's
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out MASTER_PIC_PORT,al
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mov al, CO0_EOI
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out SLAVE_PIC_PORT,al
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ret
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;================
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reset_i3tint_pic:
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;================
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;
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; Reset the interfacer 3's PIC IR line
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mov al, I3_CO_EOI ;; reset the PIC
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out MASTER_PIC_PORT,al
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ret
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;================
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reset_i3iint_pic:
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;================
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; Reset Interfacer 3's PIC
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mov al, I3_CI_EOI ;; reset the interfacer 3's PIC
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out MASTER_PIC_PORT, al ;; interrupt line
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ret
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;========
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pic_init:
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;========
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;
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; PIC initialization entry point
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;
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; interrupt structure
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;
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; MASTER PIC :
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; IRQ0 =
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; IRQ1 = DISK 2
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; IRQ2 = interfacer 3 receive ready
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; IRQ3 = interfacer 3 transmit ready
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; IRQ4 = DISK 1
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; IRQ5 =
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; IRQ6 =
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; IRQ7 = Slave input
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;
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; SLAVE PIC :
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; IRQ0 = 8087
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; IRQ1 = Timer 0 ( mpm's tick )
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; IRQ2 = Timer 1 ( free )
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; IRQ3 = Timer 2 ( free )
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; IRQ4 = 9511 svrq
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; IRQ5 = 9511 end
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; IRQ6 = SS Tx int
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; IRQ7 = SS Rx int
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;
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; DETAILS about the interrupt structure
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;
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; For both the master and the slave:
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; 1] 8086 mode
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; 2] the interrupt system is level-triggered
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; 3] all interrupts are masked off after the PICs are initialized
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;
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; The Master PIC:
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; 1] pic interrupt base is 40H
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; 2] IR 7 is a slave input
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;
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; The Slave PIC:
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; 1] pic interrupt base is at 48H
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mov al,MASTER_ICW_1 ;set up the master PIC
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out MASTER_PIC_PORT, al
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mov al,MASTER_ICW_2
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out MASTER_PIC_PORT + 1,al
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mov al,MASTER_ICW_3
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out MASTER_PIC_PORT + 1, al
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mov al,MASTER_ICW_4
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out MASTER_PIC_PORT + 1, al
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mov al,DISABLE_INTS
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out MASTER_PIC_PORT + 1, al
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mov al,SLAVE_ICW_1 ; set up the slave PIC
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out SLAVE_PIC_PORT, al
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mov al,SLAVE_ICW_2
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out SLAVE_PIC_PORT + 1,al
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mov al,SLAVE_ICW_3
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out SLAVE_PIC_PORT + 1, al
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mov al,SLAVE_ICW_4
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out SLAVE_PIC_PORT + 1, al
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mov al, DISABLE_INTS
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out SLAVE_PIC_PORT + 1, al
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ret
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;==========
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int_enable:
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;==========
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;
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; Interrupt enable entry point
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;
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; The hard disk, and all usart transmitters are not
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; enabled until they are needed.
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mov al, MASTER_INT_MASK
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out MASTER_PIC_PORT + 1, al
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mov al,SLAVE_INT_MASK
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out SLAVE_PIC_PORT + 1, al
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ret
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;============
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hard_int_vec:
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;============
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;
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; Hardware interrupt vector initialization entry point
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;
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; set DS to the interrupt vector area
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push ds ; save incoming DS
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xor ax,ax ; point to the vectors
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mov ds, ax
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; setup character i/o interrupt addr
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; console input slave irq 7 ( int 4fh )
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mov word ptr .CON_IN_OFF, offset conin_int
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mov word ptr .CON_IN_SEG, cs
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; console output slave irq 6 ( int 4eh )
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mov word ptr .CON_OUT_OFF, offset sst_int
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mov word ptr .CON_OUT_SEG, cs
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; interfacer 3 input master irq 2 ( int 42h )
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mov word ptr .I3_IN_OFF, offset i3r_int
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mov word ptr .I3_IN_SEG, cs
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; interfacer 3 output master irq 3 ( int 43h )
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mov word ptr .I3_OUT_OFF, offset i3t_int
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mov word ptr .I3_OUT_SEG, cs
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; setup hard disk i/o interrupt addr
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mov word ptr .H_DISK_OFF, offset h_disk_int
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mov word ptr .H_DISK_SEG, cs
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; setup floppy disk i/o interrupt addr (VI5)
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mov word ptr .FLPY_OFF, offset flint
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mov word ptr .FLPY_SEG, cs
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; setup tick interrupt addr
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mov word ptr .TICK_OFF, offset tick_int
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mov word ptr .TICK_SEG, cs
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if NP_8087
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; setup 8087 interrupt addr
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mov word ptr .NP_8087_OFF, offset NP_8087_int
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mov word ptr .NP_8087_SEG, cs
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endif
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pop ds ; restore the data segment
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ret
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end
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