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Digital Research
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title 'Serial Input module'
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;*****************************************
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; *
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; SERIAL INPUT MODULE *
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; Last change : 2/13/84 *
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; *
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;*****************************************
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include system.lib
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include chrcomm.equ
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include serdata.equ
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cseg
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public serial_in
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public store_char
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extrn supif:near ;; headentr.a86
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extrn ocdesctbl:word ;; serdata.a86
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extrn usart_on:near
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extrn xmit_on:near ;; servar.a86
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extrn xmit_off:near ;; servar.a86
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extrn set_bit:near ;; servar.a86
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extrn clear_bit:near ;; servar.a86
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serial_in:
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;-----
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; ENTRY: bx = addr of the input Q control block
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;
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; EXIT: al = data from the usart's Q
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; ah = the usarts status byte
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pushf ! cli
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cin2: ;; if char is available, get it
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test Q_STATE[bx], CHAR_AVAIL ;; else flagwait until it's available
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jnz cin1
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or Q_STATE[bx], IPROC_WAITING ;; set a loacal proc waiting flag
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push bx ;; save the address of Q control struc
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mov dl, SYS_FLAG[bx] ;; do the flag wait
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mov cl, F_FLAGWAIT
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call supif
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cmp ax, 0ffffh ! jne cin3 ;; was there an error ?
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mov cl, P_DISPATCH ;; dispatch the process, let it try
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call supif ;; again later
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cin3:
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pop bx ;; get back the Q control structure
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jmps cin2 ;; just in case the flagset shouldn't
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;; have happened.
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cin1:
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push bx ;; save the Q control structure
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call conin_fc ;; call the console read routine
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pop bx ;; restore the Q control addr
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mov al, LAST_CHAR[bx] ;; al = char from Q
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mov ah, LAST_STAT[bx] ;; ah = status from Q
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popf ;; turn the interrupts back on
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ret
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conin_fc:
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;;--------
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;; This routine reads a character from the console input Q
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;;
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;; ENTRY: bx -> the Q control structure
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;;
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;; EXIT: LAST_CHAR[bx] = the character that was read in
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;; LAST_STAT[bx] = the usart's status that corresponded to the
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;; char in LAST_CHAR[bx]
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push si ;; we need an index register
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mov si, PROC_OUT[bx] ;; get the Q's output index
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mov al, D_BUFF[bx+si] ;; get the character
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mov LAST_CHAR[bx], al
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mov al, S_BUFF[bx+si] ;; get the status byte
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mov LAST_STAT[bx], al
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inc si ;; inc the processes output index
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and si, (INMSGS -1) ;; mod the size of the Q
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mov PROC_OUT[bx], si ;; restore the index register
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pop si ;; restore the extra index register
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dec UN_PC[bx] ;; dec un-processed char count
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cmp UN_PC[bx], 0 ;; was this the last char in the Q ?
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jne cinf2 ;; no ...
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cinf1:
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and Q_STATE[bx], not CHAR_AVAIL
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cinf2: ;; if sender was stopped check the receive buffer
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;; for being half empty. When the receive buffer is half
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test Q_STATE[bx], SENDER_STOPPED ;; empty restart the sender
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jz cinf3
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cmp UN_PC[bx], ( INMSGS / 2 )
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ja cinf3
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call start_sender ;; the Q is half empty
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cinf3:
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ret
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store_char:
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;;----------
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;;
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;; This routine stores the status and data bytes from a usart in their Q's.
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;; It also handles the interrupt level Xon Xoff protocol.
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;; If an error is detected in the status byte returned from the USART
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;; a reset error command is sent to the usart.
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;;
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;; ENTRY: bx -> receive Q control structure
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;; al = the data read from the USART
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;; ah = the status read from the USART
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;;
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;; EXIT: the status and data are put in the status and data Q's.
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;;
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test Q_STATE[bx], BIT8_MASK ;; are we masking off the 8th bit
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jz try_xon
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and al, 7FH
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try_xon:
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test Q_STATE[bx], XX_MODE ;; is this Q in Xon Xoff mode ?
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jz store_now
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cmp al, XON ! jne try_xoff ;; is the char an Xon
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call xmit_on ;; char was an Xon, start transmitter
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ret
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try_xoff:
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cmp al, XOFF ! jne store_now
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call xmit_off ;; char was an Xoff, stop transmitter
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ret
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store_now:
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push si ;; use SI as an index register
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mov si, INT_IN[bx]
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mov D_BUFF[bx+si], al ;; store the data
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mov S_BUFF[bx+si], ah ;; store the status
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inc si
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and si, (INMSGS - 1)
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mov INT_IN[bx], si
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pop si
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or Q_STATE[bx], CHAR_AVAIL ;; set char avail flag
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test ah, PARITY_ERR or OVERRUN_ERR or FRAME_ERR;; check for usart errs
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jz no_err ;; if err, send error reset to usart
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inc ERR_CNT[bx] ;; inc the error reset counter
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mov ah, ERROR_RESET ;; set up the error reset bit
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call set_bit ;; now set it in the usarts command register
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and CMD_REG[bx], not ERROR_RESET ;; this is one time command
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;; we have to reset the command
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;; register image, so we don't
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;; keep doing an error reset
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no_err:
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inc UN_PC[bx]
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cmp UN_PC[bx], UPPER_LIM ;; is # chars in buff >= limit ?
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jb check_proc_waiting ;; no
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call stop_sender ;; yes, stop transmitter
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check_proc_waiting:
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test Q_STATE[bx], IPROC_WAITING ;; only do flagset if proc is waiting
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jz no_proc_waiting ;; for a character
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and Q_STATE[bx], not IPROC_WAITING ;; clear the process waiting flag
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push ax ! push bx ! push cx ;; this is an interrupt context
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push dx ! push bp ! push si ;; save the environment
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push di ! push es ! push ds
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sc2:
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mov dl, SYS_FLAG[bx] ;; get the flag number
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mov cl, F_FLAGSET ;; set the system function
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push bx ;; save the Q ptr in case of a retry
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call supif
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pop bx ;; restore the Q ptr
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cmp ax, 0ffffh ;; check for an error
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jne sc3
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cmp cx, 2aH ;; was it a flag ignore ?
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jne sc3 ;; if it was not an ignore just exit
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jmps sc2 ;; else, try again
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sc3:
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pop ds ! pop es ! pop di ;; restore environment
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pop si ! pop bp ! pop dx
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pop cx ! pop bx ! pop ax
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no_proc_waiting:
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ret
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start_sender:
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;;------------
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;;
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;; This routine tries to restart the sender.
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;;
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;; ENTRY: bx = addr Q control structure
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;;
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;; EXIT: none
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;;
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;; NOTE: I have assumed + 12 volts on the DSR or RTS lines means
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;; send data. Conversely - 12 volts means stop
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;; sending data.
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;; The DTR* pin (#24) on the 2651 is wired
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;; to the DSR pin on the DB-25 connector ( pin 6 ),
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;; through an inverting driver. This requires setting
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;; the DTR bit in the command register to start the sender.
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;;
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;; For the RTS protocol, the RTS* pin (23) on the 2651
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;; is wired to the Ready for Send pin on the DB-25
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;; connector ( pin 5 ) through an inverting driver. This
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;; requires setting the RTS bit in the command register
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;; to start the sender.
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test Q_STATE[bx], DTR_MODE ;; check dtr protocol
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jz try_rts1
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mov ah, DTR ;; force DTR* (dtr not) pin low
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call set_bit
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and Q_STATE[bx], not SENDER_STOPPED
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try_rts1:
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test Q_STATE[bx], RTS_MODE ;; check for RTS protocol,
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jz try_xx1
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mov ah, RTS ;; force the RTS* (rts not) pin low
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call set_bit
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and Q_STATE[bx], not SENDER_STOPPED
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try_xx1:
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test Q_STATE[bx], XX_MODE ;; check for Xon/Xoff protocol
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jz no_prot
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call send_xon
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and Q_STATE[bx], not SENDER_STOPPED
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no_prot:
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ret
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stop_sender:
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;;-----------
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;; This routine tries to stop the transmitter.
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;;
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;; ENTRY: bx = addr( Q control )
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;;
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;; EXIT: none
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;;
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test Q_STATE[bx], DTR_MODE
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jz try_rts
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mov ah, DTR ;; force DTR* (dtr not) pin high
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call clear_bit
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or Q_STATE[bx], SENDER_STOPPED
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try_rts:
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test Q_STATE[bx], RTS_MODE ;; check for RTS protocol,
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jz try_xx
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mov ah, RTS ;; force the RTS* (rts not) pin high
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call clear_bit
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or Q_STATE[bx], SENDER_STOPPED
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try_xx:
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test Q_STATE[bx], XX_MODE ;; check for Xon/Xoff protocol
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jz no_protocol
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call send_xoff
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or Q_STATE[bx], SENDER_STOPPED
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no_protocol:
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cmp UN_PC[bx], INMSGS ;; If at lim of buffer, adjust char
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jb ss_2
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ss_0:
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dec UN_PC[bx]
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cmp INT_IN[bx], 0
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je ss_1
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dec INT_IN[bx]
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jmps ss_2
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ss_1:
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mov INT_IN[bx], (INMSGS - 1) ;; force index to end of buffer
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ss_2:
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ret
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send_xon:
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;;--------
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;; This routine sends an Xon to the sender
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;;
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;; ENTRY: bx = addr of Q control sturcture
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;;
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;; EXIT: An Xon ( ctl q ) is sent to the sender
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;;
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test XINT_MASK[bx], SS_U ;; is this the system support board?
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je sxn
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mov ah, XON ;; it's interfacer 3 board
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call send_char
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sxn:
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ret
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send_xoff:
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;;---------
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;; This routine sends an Xoff to the sender.
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;;
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;; ENTRY: bx = addr of Q control sturcture
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;;
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;; EXIT: An Xoff ( ctl s ) is sent to the sender
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;;
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test XINT_MASK[bx], SS_U ;; is this the system support board?
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je sxf
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mov ah, XOFF ;; it's the interfacer 3 board
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call send_char
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sxf:
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ret
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send_char:
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;;---------
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;; This routine sends a single character to the USART in the Q ctl struct.
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;;
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;; ENTRY: bx = addr Q control structure
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;; ah = char to send
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;;
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;; EXIT: none
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push bx ;; save the input Q control addr
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mov bl, U_NUMB[bx] ;; get the usart's i3 number
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xor bh, bh ;; clear the upper byte
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inc bx ;; index above the SS usart
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shl bx, 1 ;; indexing into a word table
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mov bx, ocdesctbl[bx] ;; bx -> Output Q control
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push cx
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push si
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mov cx, OMSGCNT[bx] ;; get the number of chars in Q
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mov si, omsgout[bx] ;; get the output index
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add si, cx ;; add to it the number of chars
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and si,onmsgs-1 ;; in the buffer, mod( buff size )
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mov obuffer[bx+si],ah ;; put the char in the Q
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inc cx ;; inc the chars in Q count
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mov omsgcnt[bx],cx ;; update
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dec cx ;; if 1st char in Q, start Xmit int's
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jnz sc1 ;; cx = chars in Q - 1
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call usart_on ;; start the Xmitter
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sc1:
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pop si
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pop cx
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pop bx ;; restore the input Q control addr
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ret
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end
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