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Digital Research
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title 'Interrupt Driven Serial Variant'
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;****************************************
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; *
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; SERIAL VARIANT MODULE *
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; Last changed: 2/10/84 *
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; *
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;****************************************
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include ssboard.equ
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include i3board.equ
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include u2651.equ
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eject
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dseg
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public i3_xmit_int_vec
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public bit_mask_tbl
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extrn ocdesctbl:word
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cseg
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public char_init
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public usart_on
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public usart_off
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public usart_select
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public xmit_on
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public xmit_off
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public set_bit
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public clear_bit
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;=========
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char_init: ;; Init consoles on the System Support
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;========= and the Interfacer 3 board.
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;; do the System Support board
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MOV AL,01101110b ;; async, 16x, 8 bits, no parity,
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;; even, 1 stop
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OUT ssmode,AL ;; set up mode register 1
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MOV AL,01111110b ;; 9600 baud
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OUT ssmode,AL ;; set up mode register 2
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MOV AL,00100111b ;; trans. on, dtr low, rec. on,
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;; no break, no reset, rts low
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OUT sscmd,AL ;; set up command port
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mov dl, 0 ;; Do the Interfacer 3 board
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mov cx, 8
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i3_init_loop:
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mov al, dl
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inc dl
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call i3_init
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loop i3_init_loop
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mov al, i3_int_enable ;; turn on all I3 recv interrupts
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out I3_RCV_INT_MASK, al
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not al ;; turn off all I3 Xmit interrupts
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out I3_XMIT_INT_MASK, al
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mov i3_xmit_int_vec, al ;; initialize the bit vector
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i3_init: ;; al = uart on I3 board to init
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;; async, 16x, 8 bits, no parity,
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;; even, 1 stop, 9600 baud.
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out i3_select_reg, al
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MOV AL,01101110b
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OUT i3_uart_mode,AL ;; set up mode register 1
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MOV AL,01111110b ;; 9600 baud
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OUT i3_uart_mode,AL ;; set up mode register 2
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MOV AL,00100111b ;; Xmit on, dtr low, recv on,
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;; no break, no reset, rts low
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OUT i3_uart_cmd,AL ;; set up command port
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ret
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;========
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usart_on:
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;========
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;
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; ENTRY: bx -> Xmit Q control structure
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;
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mov al, OUSART[bx] ;; Is the usart on the i3 board ?
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cmp al, NO_SELECT
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je usrt_on1 ;; No, must be on system support board.
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mov al, 0 ;; Yes, we must first select one of the
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out I3_SELECT_REG, al ;; USARTS to get to int mask register.
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mov al, O_BIT_MASK[bx] ;; Get the USART'S mask bit
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or i3_xmit_int_vec, al ;; set our bit vector
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mov al, i3_xmit_int_vec ;; set the interfacer 3's
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out I3_XMIT_INT_MASK, al ;; interrupt mask register
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jmps usrt_on2
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usrt_on1: ;; usart is on the SS board
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in al, SLAVE_PIC_PORT + 1 ;; get the PIC mask
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and al, 0bfh ;; turn on the SS USART Xmit IR line
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out SLAVE_PIC_PORT + 1, al ;; write to the PIC
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usrt_on2:
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ret
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;=========
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usart_off:
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;=========
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;
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; ENTRY: bx -> Xmit Q control structure
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;
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cmp OUSART[bx], NO_SELECT ;; Is this the System Support board ?
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jne usrt_off1 ;; no, must be interfacer 3
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;; Turn off the Xmit interrupt at the PIC
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in al, SLAVE_PIC_PORT + 1 ;; read the PIC's mask
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or al, 40h ;; turn off the SS USART Xmit int
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out SLAVE_PIC_PORT + 1, al ;; write the mask back to the PIC
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jmps usrt_off2 ;; and exit
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usrt_off1: ;; the Xmit Q is empty and the USART
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;; is on the interfacer 3.
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mov ah, O_BIT_MASK[bx] ;; get the interfacer 3's interrupt
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;; mask register bit for this USART
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not ah ;; we need to AND off the bit
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mov al, i3_xmit_int_vec ;; get the interfacer 3's Xmit bit vector
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and al,ah ;; turn off this USART in our bit vector
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out I3_XMIT_INT_MASK, al ;; turn off the USART on the I3
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mov i3_xmit_int_vec, al ;; save our new bit vector
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usrt_off2:
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ret
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eject
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;============
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usart_select:
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;============
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;
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; ENTRY: al = usart number
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;
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out I3_SELECT_REG, al
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ret
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;============
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xmit_on:
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;============
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;;
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;; ENTRY: bx -> Recv Q control structure
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;;
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;; EXIT: The Interfacer 3's USART transmit intvec is enabled.
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;; The USART number (U_NUMB) in the Q control structure is set.
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pushf ! cli ;; interrupts off
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mov al, 0 ;; We have to select a USART on the
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out I3_SELECT_REG, al ;; interfacer 3 before we can query
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;; the interrupt status register.
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mov al, i3_xmit_int_vec ;; get the Xmit interrupt vector
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or al, XINT_MASK[bx] ;; set this Usart's interrupt bit
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mov i3_xmit_int_vec, al ;; in the Xmit interrupt vector
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out I3_XMIT_INT_MASK, al ;; and the interfacer 3's
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;; interrupt mask port
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push bx ;; save the input Q control addr
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mov bl, U_NUMB[bx] ;; get the usarts i3 number
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xor bh, bh ;; clear the upper byte
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inc bx ;; index above the SS usart
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shl bx, 1
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mov bx, ocdesctbl[bx] ;; get the output Q control addr
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and OFLAG[bx], not XOFF_PENDING ;; turn off the Xoff pending flag
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pop bx ;; restore the input Q control addr
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popf ;; turn the interrrupts back on
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ret
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;============
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xmit_off:
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;============
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;;
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;; ENTRY: bx -> Recv Q control structure
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;;
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;; EXIT: The Interfacer 3's USART transmit intvec is disabled.
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;; The USART number (U_NUMB) in the Q control structure is reset.
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;; The Xoff pending flag is set in the output Q control
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;; structure.
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pushf ! cli ;; interrupts off
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mov al, 0 ;; We have to select a USART on the
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out I3_SELECT_REG, al ;; interfacer 3 before we can query
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;; the interrupt status register.
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mov al, i3_xmit_int_vec ;; get the Xmit interrupt vector
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mov ah, XINT_MASK[bx] ;; get the Usarts interrupt bit
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not ah ;; reset this Usart's interrupt bit
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and al, ah ;; in the Xmit interrupt vector
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mov i3_xmit_int_vec, al ;; and the interfacer 3's
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out I3_XMIT_INT_MASK, al ;; interrupt mask port
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push bx ;; save the input Q control addr
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mov bl, U_NUMB[bx] ;; get the usarts i3 number
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xor bh, bh ;; clear the upper byte
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inc bx ;; index above the SS usart
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shl bx, 1
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mov bx, ocdesctbl[bx] ;; get the output Q control addr
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or OFLAG[bx], XOFF_PENDING ;; turn on the Xoff pending flag
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pop bx ;; restore the input Q control addr
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popf ;; turn the interrrupts back on
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ret
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;============
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set_bit:
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;============
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;; ENTRY: ah = Bit to set in the Q state word
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;; bx -> Recv Q control structure
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;;
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;; EXIT: CMD_REG[bx] and the Usart's command register
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;; have the bits specified in ah set
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push dx
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pushf ! cli ;; synchronize command register images
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mov al, U_NUMB[bx] ;; get the USART's number on the I3 bd
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cmp al, SS_U ;; select the usart if it's on the
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je set_bit1 ;; interfacer 3 board
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out I3_SELECT_REG, al ;; do the select
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set_bit1:
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mov al, CMD_REG[bx] ;; get the command resgisters image
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or al, ah ;; or in the bit(s)
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mov CMD_REG[bx], al ;; put back the new image
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xor dh,dh
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mov dl, U_PORTC[bx] ;; get the command port address
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out dx, al ;; send this image to the usart
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popf
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pop dx
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ret
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;=========
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clear_bit:
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;;========
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;;
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;; ENTRY: ah = Bit to clear in the Q state word
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;; bx -> Recv Q control structure
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;;
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;; EXIT: Q_STATE[bx] and the Usart's command register
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;; have the bits specified in ah cleared.
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push dx
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pushf ! cli ;; synchronize command register images
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mov al, U_NUMB[bx] ;; get the USART's number on the I3 bd
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cmp al, SS_U ;; select the usart if it's on the
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je clr_bit1 ;; interfacer 3 board
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out I3_SELECT_REG, al ;; do the select
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clr_bit1:
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mov al, CMD_REG[bx] ;; get the command resgisters image
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not ah ;; create the AND mask
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and al, ah ;; AND off the bits specfied
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mov CMD_REG[bx], al ;; put back the new image
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xor dh,dh
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mov dl, U_PORTC[bx] ;; get the command port address
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out dx, al ;; send this image to the usart
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popf
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pop dx
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ret
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dseg
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i3_xmit_int_vec db 0
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bit_mask_tbl db 80h, 40h, 20h, 10h, 08h, 04h, 02h, 01h
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end
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