;************************************************
;*	Interfacer 3 board euqate module	*
;*	File Name: I3BOARD.EQU			*
;*	Last Update: 10/11/83			*
;************************************************

; Interfacer 3 board port definitions

i3_base		        equ	10h		; base addr of board
i3_uart_data		equ	i3_base	        ; usart data port
i3_uart_status	        equ	i3_base + 1	; usart status port
i3_uart_mode		equ	i3_base + 2	; usart mode port
i3_uart_cmd		equ	i3_base + 3	; usart command port
i3_xmit_int_stat	equ	i3_base + 4	; I3 Xmit Interrupt status
i3_xmit_int_mask	equ	i3_base + 4	; I3 Xmit Interrupt mask
i3_rcv_int_stat	        equ	i3_base + 5	; I3 Recv Interrupt status
i3_rcv_int_mask	        equ	i3_base + 5	; I3 Recv Interrupt mask
i3_select_reg		equ	i3_base + 7	; I3 Usart Select register


; The I3 board has two Interrupt mask registers to control which
; usarts (0-7) interrupt systems are enabled.
; One mask register is for Xmit the other for Recv.
; When the interrupt mask ports are read, they act as status ports.
; A Usart that has its interrupt disabled will have a 0 in its
; corresponding bit position. Usart 0 = bit 0, Usart 7 = bit 7.
; The quiescent state is: All receiver interrupts are enabled. An
; Xmit interrupt is only enabled when the Xmitter is in use.

I3_INT_ENABLE		equ	0ffH	; receive interrupt mask 

; The following equates are for the Xmit Q control stuctures.

OFLAG		equ	byte ptr 1	; Queue control flags
OUSART		equ	byte ptr 8	; Usart number 
O_BIT_MASK	equ	byte ptr 10	; Usarts Int register mask bit

; Flag bit(s) for OFLAG field in Xmit Q control structure

XOFF_PENDING	equ	10H		; set = Xoff received from the guy
					; were sending data to.

; The following equates are for the Recv Q control stucture

U_NUMB		equ	byte ptr 10	; Usarts number
CMD_REG		equ	byte ptr 3	; Usart command register image
U_PORTC		equ	byte ptr 11	; Usart Command port
XINT_MASK	equ	byte ptr 14	; Bit(s) used as the Xmit ready mask