mirror of
https://github.com/SEPPDROID/Digital-Research-Source-Code.git
synced 2025-10-22 16:04:18 +00:00
99 lines
3.9 KiB
C
99 lines
3.9 KiB
C
/*
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* @(#)asz8k.h 3.1
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*
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* Declarations specific to asz8k.
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*/
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/*
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* Parameters.
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*/
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#define OPMAX 4 /* maximum number of instruction operands */
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/*
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* Instruction format table flags (in fm_flg).
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*/
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#define FMNIB7 0x000f /* value to OR into nibble 7 */
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#define FMSKEL2 0x0010 /* generate 2nd skeleton word */
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#define FMNEGI 0x0020 /* negate immediate value for right shift */
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#define FMLAST 0x8000 /* final entry for this instruction */
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/*
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* Operand actions (in fm_op[]).
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*/
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#define OANULL 0x0000 /* operand not used */
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#define OANIB1 0x0100 /* pack into nibble 1 */
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#define OANIB2 0x0200 /* pack into nibble 2 */
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#define OANIB3 0x0300 /* pack into nibble 3 */
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#define OANIB5 0x0500 /* pack into nibble 5 */
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#define OANIB6 0x0600 /* pack into nibble 6 */
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#define OANIB7 0x0700 /* pack into nibble 7 */
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#define OABYT1 0x0800 /* pack into byte 1 */
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#define OAX2 0x0900 /* generate indexed addr using nibble 2 */
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#define OAX3 0x0a00 /* generate indexed addr using nibble 3 */
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#define OABA2 0x0b00 /* generate based address using nibble 2 */
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#define OABA3 0x0c00 /* generate based address using nibble 3 */
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#define OABX2 0x0d00 /* generate based-indexed addr using nibble 2 */
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#define OABX3 0x0e00 /* generate based-indexed addr using nibble 3 */
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#define OACFLAG 0x0f00 /* OR condition flag bit into nibble 2 */
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#define OANIB3S 0x1100 /* pack into low 3 bits of nibble 3 */
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#define OANIB3A 0x1200 /* AND into nibble 3 */
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#define OANIB3D 0x1300 /* decrement and pack into nibble 3 */
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#define OANIB7D 0x1700 /* decrement and pack into nibble 7 */
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#define OARA7 0x1800 /* generate 7-bit relative address */
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#define OARA8 0x1900 /* generate 8-bit relative address */
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#define OARA12 0x1a00 /* generate 12-bit relative address */
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#define OARA16 0x1b00 /* generate 16-bit relative address */
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#define OAIMM8 0x1c00 /* generate 8-bit immediate */
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#define OAIMM16 0x1d00 /* generate 16-bit immediate */
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#define OAIMM32 0x1e00 /* generate 32-bit immediate */
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#define OASHFT 0x1f00 /* generate shift count of 1 or 2 */
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#define OAMSK 0x1f00 /* mask for operand action field */
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/*
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* Operand classes.
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*/
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#define OCREG8 0x0004 /* {rh0,rh1,rh2,rh3,...,rl4,rl5,rl6,rl7} */
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#define OCREG16 0x0005 /* {r0,r1,r2,r3,...,r14,r15} */
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#define OCREG32 0x0006 /* {rr0,rr2,rr4,rr6,rr8,rr10,rr12,rr14} */
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#define OCREG64 0x0007 /* {rq0,rq4,rq8,rq12} */
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#define OCIMM 0x0008 /* immediate value */
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#define OCIR 0x0009 /* indirect register */
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#define OCX 0x000a /* indexed address */
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#define OCBA 0x000b /* based address */
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#define OCBX 0x000c /* based-indexed address */
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#define OCCCODE 0x000d /* condition code */
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#define OCCFLAG 0x000e /* condition code flag bit */
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#define OCINT 0x000f /* {nvi,vi} */
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#define OCCTL 0x0010 /* control register for LDCTL */
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#define OCFLAGS 0x0011 /* FLAGS for LDCTLB */
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#define OCIRIO 0x0012 /* indirect register for I/O instruction */
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#define OCREGA 0x0013 /* address register (depends on seg mode) */
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#define OCMSK 0x001f /* mask for operand class field in fm_op */
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/*
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* Operand flags (in op_flg and ps_flg).
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*/
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#define OFXMSK 0x0f /* mask for index register code */
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#define OFSHORT 0x80 /* force short offset */
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/*
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* Token types.
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*/
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#define TKPOUND 14 /* '#' */
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#define TKAT 15 /* '@' */
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#define TKREG8 16 /* {rh0,rh1,rh2,rh3,...rl4,rl5,rl6,rl7} */
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#define TKREG16 17 /* {r0,r1,r2,r3,...,r12,r13,r14,r15} */
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#define TKREG32 18 /* {rr0,rr2,rr4,rr6,rr8,rr10,rr12,rr14} */
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#define TKREG64 19 /* {rq0,rq4,rq8,rq12} */
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#define TKCCODE 20 /* condition codes and flags */
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#define TKINT 21 /* {nvi,vi} */
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#define TKCTL 22 /* control registers for LDCTL */
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#define TKFLAGS 23 /* FLAGS for LDCTLB */
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/*
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* Structure declarations.
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*/
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struct format { /* instruction format table entry */
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int fm_op[OPMAX]; /* operand descriptions */
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int fm_skel; /* opcode skeleton word */
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int fm_flg; /* flags */
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};
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/*
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* Global variable declarations.
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*/
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char segflg; /* Generate code for segmented processor */
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