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50 lines
2.0 KiB
Plaintext
50 lines
2.0 KiB
Plaintext
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;************************************************
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;* Interfacer 3 board euqate module *
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;* File Name: I3BOARD.EQU *
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;* Last Update: 10/11/83 *
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;************************************************
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; Interfacer 3 board port definitions
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i3_base equ 10h ; base addr of board
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i3_uart_data equ i3_base ; usart data port
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i3_uart_status equ i3_base + 1 ; usart status port
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i3_uart_mode equ i3_base + 2 ; usart mode port
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i3_uart_cmd equ i3_base + 3 ; usart command port
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i3_xmit_int_stat equ i3_base + 4 ; I3 Xmit Interrupt status
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i3_xmit_int_mask equ i3_base + 4 ; I3 Xmit Interrupt mask
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i3_rcv_int_stat equ i3_base + 5 ; I3 Recv Interrupt status
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i3_rcv_int_mask equ i3_base + 5 ; I3 Recv Interrupt mask
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i3_select_reg equ i3_base + 7 ; I3 Usart Select register
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; The I3 board has two Interrupt mask registers to control which
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; usarts (0-7) interrupt systems are enabled.
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; One mask register is for Xmit the other for Recv.
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; When the interrupt mask ports are read, they act as status ports.
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; A Usart that has its interrupt disabled will have a 0 in its
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; corresponding bit position. Usart 0 = bit 0, Usart 7 = bit 7.
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; The quiescent state is: All receiver interrupts are enabled. An
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; Xmit interrupt is only enabled when the Xmitter is in use.
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I3_INT_ENABLE equ 0ffH ; receive interrupt mask
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; The following equates are for the Xmit Q control stuctures.
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OFLAG equ byte ptr 1 ; Queue control flags
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OUSART equ byte ptr 8 ; Usart number
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O_BIT_MASK equ byte ptr 10 ; Usarts Int register mask bit
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; Flag bit(s) for OFLAG field in Xmit Q control structure
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XOFF_PENDING equ 10H ; set = Xoff received from the guy
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; were sending data to.
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; The following equates are for the Recv Q control stucture
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U_NUMB equ byte ptr 10 ; Usarts number
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CMD_REG equ byte ptr 3 ; Usart command register image
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U_PORTC equ byte ptr 11 ; Usart Command port
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XINT_MASK equ byte ptr 14 ; Bit(s) used as the Xmit ready mask
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