mirror of
https://github.com/SEPPDROID/Digital-Research-Source-Code.git
synced 2025-10-24 08:54:17 +00:00
180 lines
4.8 KiB
Plaintext
180 lines
4.8 KiB
Plaintext
|
||
;I/O port definitions
|
||
|
||
;DMA controller (i8237-2) ports
|
||
DMAC_BADD0 EQU 00H ;Channel 0 - base & current address (write)
|
||
DMAC_CADD0 EQU 00H ; " " - current address (read)
|
||
DMAC_BCNT0 EQU 01H ; " " - base & current word count (write)
|
||
DMAC_CCNT0 EQU 01H ; " " - curent word count (read)
|
||
DMAC_BADD1 EQU 02H ;Channel 1 - base & current address (write)
|
||
DMAC_CADD1 EQU 02H ; " " - current address (read)
|
||
DMAC_BCNT1 EQU 03H ; " " - base & current word count (write)
|
||
DMAC_CCNT1 EQU 03H ; " " - curent word count (read)
|
||
DMAC_BADD2 EQU 04H ;Channel 2 - base & current address (write)
|
||
DMAC_CADD2 EQU 04H ; " " - current address (read)
|
||
DMAC_BCNT2 EQU 05H ; " " - base & current word count (write)
|
||
DMAC_CCNT2 EQU 05H ; " " - curent word count (read)
|
||
DMAC_BADD3 EQU 06H ;Channel 3 - base & current address (write)
|
||
DMAC_CADD3 EQU 06H ; " " - current address (read)
|
||
DMAC_BCNT3 EQU 07H ; " " - base & current word count (write)
|
||
DMAC_CCNT3 EQU 07H ; " " - curent word count (read)
|
||
DMAC_STAT EQU 08H ;Status register (read)
|
||
DMAC_CMD EQU 08H ;Command register (write)
|
||
DMAC_REQ EQU 09H ;Request register (write)
|
||
DMAC_MASK_SR EQU 0AH ;Single mask register bit (write)
|
||
DMAC_MODE EQU 0BH ;Mode register (write)
|
||
DMAC_FLOP EQU 0CH ;Clear byte pointer flip/flop (write)
|
||
DMAC_TEMP EQU 0DH ;Temporary register (read)
|
||
DMAC_CLR EQU 0DH ;Master clear (write)
|
||
DMAC_MASK EQU 0FH ;All mask register bits (write)
|
||
|
||
;Programmable interrupt controller (i8259A) ports
|
||
PIC_STAT EQU 010H ;Interrupt request/serviced status
|
||
PIC_ICW EQU 010H ;Initialization control words
|
||
PIC_IMR EQU 011H ;Interrupt level masks
|
||
PIC_OCW EQU 011H ;Operational control words
|
||
|
||
;DIP switch and diagnostic LED display
|
||
DIP_SW EQU 020H ;DIP switch
|
||
LED_DSPY EQU 020H ;LED display
|
||
|
||
;Bank select registers
|
||
DMAC_BANK EQU 30H ;general - before separate ones used
|
||
FDC_BANK EQU 31H ;Floppy bank
|
||
REFRESH_BANK EQU 30H ;Refresh bank
|
||
SIO_BANK EQU 32H ;SIO bank - for networking
|
||
WINCH_BANK EQU 33H ;Winchester bank
|
||
Z80_BANK EQU 30H ;Z80 bank
|
||
|
||
;CRT controller
|
||
CRT_ADDR EQU 040H ;Address/status register
|
||
CRT_STAT EQU 040H
|
||
CRT_DATA EQU 041H ;Register file
|
||
CRT_CHAR EQU 020H ;Character latch
|
||
|
||
;Floppy disk controller ports
|
||
AUX_CMD EQU 050H ;Floppy disk select/handshake
|
||
FDC_CMD EQU 060H ;Command port
|
||
FDC_STAT EQU 060H ;Status register
|
||
FDC_TRK EQU 061H ;Track register
|
||
FDC_SEC EQU 062H ;Sector register
|
||
FDC_DATA EQU 063H ;Data register
|
||
|
||
;Keyboard
|
||
KYBD_DATA EQU 051H ;Keyboard data
|
||
KYBD_STAT EQU 052H ;Keyboard Status
|
||
KYBD_CNTL EQU 053H ;Mode control 8255
|
||
BUZZER EQU 050H ;Buzzer
|
||
|
||
;Hard disk registers
|
||
ADP_STAT EQU 071H
|
||
ADP_CMD EQU 071H
|
||
ADP_DIAG EQU 072H
|
||
ADP_DATA EQU 073H
|
||
|
||
;Programmable interval timer (i8253) ports
|
||
PIT0_CT0 EQU 080H ;PIT 0, counter 0
|
||
PIT0_CT1 EQU 081H ; " 0, " 1
|
||
PIT0_CT2 EQU 082H ; " 0, " 2
|
||
PIT0_CTL EQU 083H ; " 0, control
|
||
PIT1_CT0 EQU 090H ; " 1, counter 0
|
||
PIT1_CT1 EQU 091H ; " 1, " 1
|
||
PIT1_CT2 EQU 092H ; " 1, " 2
|
||
PIT1_CTL EQU 093H ; " 1, control
|
||
|
||
;Serial input/output (Z80-SIO) ports
|
||
SIO0A_DATA EQU 0A0H ;SIO 0, channel A, data
|
||
SIO0A_STAT EQU 0A1H ; " 0, " A, status
|
||
SIO0A_CNTL EQU 0A1H ; " 0, " A, control
|
||
SIO0B_DATA EQU 0A2H ;SIO 0, channel B, data
|
||
SIO0B_STAT EQU 0A3H ; " 0, " B, status
|
||
SIO0B_CNTL EQU 0A3H ; " 0, " B, control
|
||
SIO1A_DATA EQU 0B0H ;SIO 1, channel A, data
|
||
SIO1A_STAT EQU 0B1H ; " 1, " A, status
|
||
SIO1A_CNTL EQU 0B1H ; " 1, " A, control
|
||
SIO1B_DATA EQU 0B2H ;SIO 1, channel B, data
|
||
SIO1B_STAT EQU 0B3H ; " 1, " B, status
|
||
SIO1B_CNTL EQU 0B3H ; " 1, " B, control
|
||
|
||
SIO_INT_VEC EQU 0E0H ;Interrupt vector - SIO or DART
|
||
|
||
;Centronics compatible parallel printer ports
|
||
PTR_DATA EQU 0F0H ;Printer data out
|
||
PTR_STAT EQU 0F1H ; " status
|
||
PTR_CNTL EQU 0F2H ; " control
|
||
PTR_MODE EQU 0F3H ; " port mode control
|
||
PTR_FLAG EQU PTR_MODE
|
||
|
||
;LED display constants
|
||
led_0 equ 0c0h
|
||
led_1 equ 0f9h
|
||
led_2 equ 0a4h
|
||
led_3 equ 0b0h
|
||
led_4 equ 099h
|
||
led_5 equ 092h
|
||
led_6 equ 082h
|
||
led_7 equ 0f8h
|
||
led_8 equ 080h
|
||
led_9 equ 098h
|
||
|
||
led_0p equ 040h
|
||
led_1p equ 079h
|
||
led_2p equ 024h
|
||
led_3p equ 030h
|
||
led_4p equ 019h
|
||
led_5p equ 012h
|
||
led_6p equ 002h
|
||
led_7p equ 078h
|
||
led_8p equ 000h
|
||
led_9p equ 018h
|
||
|
||
;Others
|
||
LINE_LENGTH EQU 80 ;Length of CRT character line
|
||
CR EQU 13
|
||
LF EQU 10
|
||
BS EQU 08
|
||
ESC EQU 1BH
|
||
NULL EQU 0
|
||
BELL EQU 7
|
||
INT3 EQU 0CCH
|
||
CNTL_X EQU 'X'-'A'+1
|
||
CNTL_Q EQU 'Q'-'A'+1
|
||
CNTL_Z EQU 'Z'-'A'+1
|
||
CNTL_S EQU 'S'-'A'+1
|
||
TRUE EQU -1
|
||
FALSE EQU 0
|
||
|
||
RD_CMD EQU 20H ;Read command for FLOPALL
|
||
WR_CMD EQU 50H ;Write with verify
|
||
|
||
BIT0 EQU 00000001B
|
||
BIT1 EQU 00000010B
|
||
BIT2 EQU 00000100B
|
||
BIT3 EQU 00001000B
|
||
BIT4 EQU 00010000B
|
||
BIT5 EQU 00100000B
|
||
BIT6 EQU 01000000B
|
||
BIT7 EQU 10000000B
|
||
|
||
;Equivalent to JNZ $+3 ; RET
|
||
|
||
CodeMacro RZ
|
||
DB 75H
|
||
DB 01H
|
||
DB 0C3H
|
||
EndM
|
||
|
||
;Equivalent to JZ $+3 ; RET
|
||
|
||
CodeMacro RNZ
|
||
DB 74H
|
||
DB 01H
|
||
DB 0C3H
|
||
EndM
|
||
|
||
RE EQU RZ
|
||
RNE EQU RNZ
|
||
JC EQU JB
|
||
JNC EQU JNB
|
||
JNBE EQU JA
|
||
|