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126 lines
2.6 KiB
Plaintext
126 lines
2.6 KiB
Plaintext
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title 'Intel 8253 CTC module'
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;************************************************
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; *
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; COUNTER TIMER CHIP MODULE *
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; Last changed : 12/15/83 *
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; *
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;************************************************
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include system.lib
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LATENCY equ false ; if the CTC is programmed for modes
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; 2 or 3 then set this to true.
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; COUNTER TIMER EQUATES
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TIMER0_CTL_WORD EQU 30H ; timer 0, two byte rl, mode 0
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TIMER0_LB EQU 3CH
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TIMER0_HB EQU 82H
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TIMER0_LATCH EQU 0
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TIMER0_RESET_COUNT EQU 823CH
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;
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; these are the compupro CTC PORT ADDRESSES
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CTC_PORT_BASE equ 50H
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CTC_CTL_PORT equ ctc_port_base + 7
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Timer_0 equ ctc_port_base + 4
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cseg
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public ctc_init
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public reset_tick_ctc ; called by the tick module
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public int_latency ; called by the tick module
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;
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; now set up the timer for 16.67 milliseconds
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; timer 0, two byte rl, mode 0
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;========
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ctc_init:
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;==============
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reset_tick_ctc:
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;==============
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;
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; At this time the CTC is only used to generate the real time tick
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; for CCP/M. Therefore initing and reseting the tick do the same thing.
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;
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mov al, TIMER0_CTL_WORD ; select timer 0 mode 0
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out CTC_CTL_PORT, al ; two byte count
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mov al,TIMER0_LB ; load the LSB
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out timer_0, al
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mov al, TIMER0_HB ; load the MSB
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out timer_0, al
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; at this point the CTC starts counting
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ret
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;===========
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int_latency:
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;===========
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; Interrupt latency measurement entry point.
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;
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; ENTRY: from the tick interrupt service routine
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;
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; EXIT: max_latency is updated if the current latency is
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; greater than any previous latency since cold boot.
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;
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; NOTE: all registers are preserved, two levels ( 4 bytes )
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; of stack are used.
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if not LATENCY
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ret
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endif
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if LATENCY
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push ax ; save the CPU environment we're
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push dx ; going to use
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mov al, TIMER0_LATCH ; latch the timer's count
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out CTC_CTL_PORT, al
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in al, TIMER_0 ; get the timers lsb
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mov ah, al ; store it
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in al, TIMER_0 ; get the timers msb
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xchg ah, al ; arrange the CTC's latched count
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; as a 16 bit word
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mov dx, TIMER0_RESET_COUNT ; subtract the initialization count
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sub dx, ax ; from the count just read
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cmp dx, max_latency
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jbe no_latency_update
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; the latency just measure is the
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; worst case
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mov max_latency, dx ; update maximum latency read so far
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no_latency_update:
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pop dx ; restore the CPU environment
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pop ax
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ret
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endif
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dseg
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max_latency dw 0
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end
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